1) Field of the Invention
The present invention relates to a semiconductor testing circuit and a semiconductor testing method for performing tests of writing or reading operations of a semiconductor storage device, and a semiconductor storage device comprising such a semiconductor testing circuit.
2) Description of the Related Art
The recent movement toward downsizing of electronic devices requires reduction in areas which semiconductor devices occupy in the electronic devices. In addition, in a growing number of cases including the cases of MCPs (Multichip Packages) and SIPs (System in Packages), a plurality of semiconductor chips are arranged in a single package.
For example, devices in which semiconductor storage devices such as DRAMs (Dynamic Random Access Memories) are mounted in MCPs and SIPs are also increasing. In the case of semiconductor storage devices, it is important to detect a defective bit in memory cells during a testing step before shipment. However, in many cases where semiconductor storage devices are mounted in an MCP or SIP, wirings connecting the semiconductor storage devices and other chips are closed within each package. Since, in the above cases, no control terminals of the semiconductor storage devices are provided as external terminals of the packages, it is impossible to perform a test after the semiconductor storage devices and the chips are sealed in the package.
Therefore, it has been proposed to arrange a testing circuit within a chip in which a semiconductor circuit to be tested is arranged, or in another chip which is built in the same package as the chip in which the semiconductor circuit to be tested is arranged, and replace a portion of testing steps with operations of the testing circuit. Such a function being arranged in a package in which a semiconductor circuit to be tested is arranged, and performing a test of the semiconductor circuit is called BIST (Built-In Self Test).
In a typical example of conventional semiconductor storage devices in which a circuit for realizing the BIST function (hereinafter referred to as a BIST circuit) is arranged, a memory cell array divided into a plurality of banks or cell array units and self-testing circuits (corresponding to the BIST circuit) respectively provided for the plurality of banks or cell array units are provided, where the self-testing circuits can be individually controlled. Each of the self-testing circuits comprises: an address generation circuit, a test-pattern-data generation circuit, and a control-signal generation circuit which are associated with the corresponding bank or cell array unit; a BIST control circuit which controls the address generation circuit, the test-pattern-data generation circuit, and the control-signal generation circuit; and comparators which compare data outputted from the corresponding bank or cell array unit during a test with expected values, and the number of which corresponds to the number of output bits of the corresponding bank or cell array unit.
In the above semiconductor storage device, the BIST control circuit operates in response to input of a system clock signal into the BIST control circuit. Under the control of the BIST control circuit, the address generation circuit, the test-pattern-data generation circuit, and the control-signal generation circuit respectively output addresses, test patterns, and control signals for write, readout, and the like, where the addresses, test patterns, and control signals are necessary for the test. Thus, when the memory cell array receives the addresses, test patterns, and control signals, writing and reading operations are performed in the memory cell array. Then, the comparators compare data outputted from the memory cell array by the reading operation with expected values, and determines a pass or fail (see, for example, Japanese Unexamined Patent Publication No. 2002-163899, paragraph Nos. 0009 to 0023 and FIG. 1).
Incidentally, the BIST circuits normally enable execution of more than one type of test patterns which are prepared in advance. For example, each test pattern is designed so that areas in which data are stored in the memory cell array form a geometrical pattern. In addition, combinations of written data and increments in the designated address are changed according to necessity.
FIG. 18 is a diagram illustrating an example of assignment of logical addresses for a memory cell array. In the example of FIG. 18, it is possible to designate a logical address of a memory cell array by a numerical value represented by 22 bits, where the 6 least significant bits, the 14 middle significant bits, and the 2 most significant bits indicate a column address, a row address, and a bank address, respectively. Normally, each BIST circuit comprises a counter circuit for generating write and read addresses as above.
FIG. 19 is a diagram illustrating an exemplary construction of a conventional address counter provided in a BIST circuit. The address counter of FIG. 19 is provided in correspondence with the address assignment of FIG. 18, and has 22 counter cells CNT0 to CNT21 corresponding to the number of bits representing the address. Specifically, the 6 least significant counter cells CNT0 to CNT5, the 14 middle significant counter cells CNT6 to CNT19, and the 2 most significant counter cells CNT20 and CNT21 are assigned to the column address CA0 to CA5, the row address RA0 to RA13, and the bank address BA0 to BA1, respectively. When the values outputted from the address counter are decoded, for example, by an address decoder, a bit line, a word line, and a bank are selected.
In the above address counter, the value of each of the counter cells CNT1 to CNT21 above the least significant counter cell CNT0 is incremented according to the output of a counter cell located immediately below each counter cell. When an increment control signal (e.g., a clock signal CLK) is applied to the least significant counter cell CNT0, a counting operation is started.
In the case where data is written in all memory cells by a self-testing operation of a BIST circuit (hereinafter referred to as a BIST operation), normally the following operations are performed.
At the beginning of the BIST operation, the counter cells are generally in a reset state, i.e., all of the column address, the row address, and the bank address are zero. When the first writing operation is performed with the above values of the column address, the row address, and the bank address, data is written in a memory cell having the address value “0.” Next, the count by the address counter is incremented, and the least significant counter bit of the output of the address counter becomes “1.” Thus, the second writing operation is performed with the incremented value of the column address, data is written in a memory cell having the address value “1.” Thereafter, every time a writing operation is performed, the count by the address counter is incremented, so that data can be written in all of the memory cells.
Further, a self-testing circuit for performing a test of RAMs having different shapes and being arranged within an integrated circuit has been proposed (see, for example, Japanese Unexamined Patent Publication No. 2001-222900, paragraph Nos. 0010 to 0030 and FIG. 1). The self-testing circuit comprises an X-address register, a Y-address register, and a chip-enable-control circuit. The X-address register and the Y-address register are each constituted by an up counter and registers, and respectively generate X-addresses and Y-addresses for all of RAMs to be tested. The chip-enable-control circuit generates and outputs enable signals for the RAMs to be tested, based on the X-addresses and Y-addresses outputted from the X-address register and the Y-address register. In the self-testing circuit, the chip-enable-control circuit recognizes the shape of each RAM to be tested, based on the numbers of bits of the X-addresses and Y-addresses outputted from the X-address register and the Y-address register. Therefore, it is possible to share a data generation circuit which generates diagonal patterns, and perform tests of the circuits in parallel.